Applied Engineers New Materials For AI And The ‘Angstrom Era’ Of Chips (2024)

It’s always fun for me to learn about a new technology, whether it’s a wearable that tracks my vital signs, a better laptop with on-device AI, a new piece of enterprise software that helps me run my business or some innovation in the datacenter that’s going to make cloud-based services faster and better. But as a former longtime semiconductor exec, I feel a special fascination for the science and engineering that goes into chips and the equipment that makes them.

Applied Materials has been an 800-pound gorilla of the chip equipment space for decades, and it has retained its prominence in no small part because of the complexity of the fundamental research it carries out to solve practical problems and advance the field. In a chip company, your colleague with a Ph.D. probably studied electrical engineering; at Applied Materials, your friend Dr. So-and-so is more likely to have a Ph.D. in materials science or chemical engineering.

At the Semicon West conference held in San Francisco earlier this month, the company really lived up to its name by rolling out two new engineered materials that will help chipmakers go to the 2nm production node and below. More than that, the Applied leaders and researchers who spoke showed how these innovations—and all the work Applied does—tie directly to the technology revolutions underway in data, AI, electric vehicles, renewable energy and more.

AI And Other Macro Trends Affecting Chip Production

At the event, Michael Sullivan, who leads investor relations for Applied, kicked things off by reviewing key steps in the evolution of the company’s thinking about market needs over the past decade. By 2016, leaders at Applied sensed that AI and IoT would be major drivers of growth. Since then—and keep in mind this is only eight years later—the chip equipment market has tripled.

By 2018, Applied, along with Nvidia and others, was paying close attention to how deep learning might reshape industries—as indeed it has with the explosion of generative AI over the past couple of years. In line with this, that year (not coincidentally at the Semicon West conference) Applied CEO Gary Dickerson spoke of the need for a 1,000x improvement in performance-per-watt, along with a new chip design playbook that included new chip architectures such as GPUs and TPUs, breakthrough materials, 3-D designs and other advances to counteract the slowing of Moore’s law that had been taking place. He was right, and Applied is following that playbook today.

Next up on the dais was Dr. Prabu Raja, president of the company’s Semiconductor Products Group. He walked the audience through some of today’s fundamental macro trends affecting the chip industry—and by extension the chip equipment industry. (His doctorate is in plasma physics, by the way.)

Raja focused on AI and reeled off some figures that I still find stunning even though I marinate in this stuff all the time. Datacenter AI is projected to be an $8 trillion market by 2030. Edge AI and IoT, $2 trillion. EVs and autonomous vehicles, a mere $1.5 trillion. Renewable energy, $4.5 trillion. It’s worth repeating the obvious: not only will all of these sectors need far more chips—they’ll need better chips.

If we look backward instead of forward, we see that the exponential growth of LLMs means that in the past five years, compute used to train AI models has grown by a factor of 10,000. Even more impressive to me is that the number of chips performing that compute has grown by “only” 100x, which is a testament to how effective the chips are. The bad news is that the energy consumption of those chips has increased by 250x, which shows you how thirsty they are for power. As Raja rightly pointed out, that trajectory for AI energy consumption is not at all sustainable, so the industry has no choice but to pursue greater energy efficiency at the same time it builds faster, more capable chips.

Achieving that requires better semiconductor logic (and thus new transistor architecture), better DRAM (with vertical and 3-D designs), high-bandwidth memory and advanced chip packaging. Supporting these technologies requires better materials and better processes for fundamental manufacturing steps such as deposition and removal. And all of it creates complex, layered interactions, whether among the literal microscopic layers of material on each wafer, the layers of process steps that must be carried out with mind-boggling precision or the layers of technical and commercial interactions among chipmakers and their vendors of chip equipment, design software and so on.

Getting all of those interactions right is the only way you can layer five or more different engineered materials in a space only 10nm wide inside a cutting-edge chip—and replicate it across the 10 trillion transistors on a wafer.

Improving Chip Wiring With A Ruthenium-Cobalt Binary Metal Liner And An Improved Low-k Dielectric

Fortunately, Raja’s group is hard at work on various aspects of this challenge. In a related announcement made the day before Applied’s Semicon West presentation, Applied debuted two new breakthroughs in engineered materials that directly address the performance-per-watt issue by enabling copper wiring to perform at the 2nm logic node and below.

In case you’re not familiar with chip manufacturing, let me offer some simple context. The history of the semiconductor industry is punctuated with milestones where some previously ubiquitous material had to be discarded because the transistors got so small that the material was no longer useful. Just recall that in the early days of the industry, technicians used soldering irons to attach arrays of transistors the size of your thumbnail to fiberboard backings—and then extrapolate from there by about 60 years to get where we are today.

These days, parts of a chip are so infinitesimally small—in some cases, just a few atoms thick—that manufacturers run up against the limits of the physics of the material. In one very specific example, for years chip makers have been using increasingly thin barrier and liner layers that allow copper to be deposited into the tiny trenches of 3-D wiring patterns without accidentally interacting with the substrate material of the chip, which would cause various problems. But the scale is now so small that the barrier and liner materials are taking up too much of the real estate in the wiring trench, which means, in Applied’s words, “it becomes physically impossible to create low-resistance, void-free copper wiring in the remaining space.”

That is about as arcane an engineering problem as you could imagine, but I am not surprised that Applied’s materials scientists and engineers were up to the task. Using a combination of six different techniques under ultra-high-vacuum conditions, they have devised a way to deposit a precise binary combination of ruthenium and cobalt that reduces the thickness of the liner by one-third (to 2nm) at the same time that it reduces electrical resistance by up to 25% and makes it easier to fill the trench with copper—without any voids in the material that would spoil performance. (I’m a visual learner; this short video from Applied does a great job of describing the process in approachable terms.)

The other materials innovation announced at the same time is a new low-k dielectric that also lowers resistance while strengthening chips with stacked 3-D designs. One of Applied’s numerous long-running successes in the industry is its Black Diamond dielectric film, which is put around the copper wiring inside of chips to reduce electrical interference and keep power consumption low. The latest advance in the Black Diamond lineup has an even lower k-value than before, which will again enable chip manufacturing at and below the 2nm node with lower capacitance for faster signals. Even better, the dielectric material has 40% higher mechanical strength than its predecessors, which is an important advantage given the stresses on chips that are being generated by 3-D chiplet-stacking designs with more layers than ever.

It’s too much detail to go into here, but suffice it to say that both of these new materials work hand-in-hand with Applied’s chip production equipment, which is used almost ubiquitously throughout the semiconductor industry. Unsurprisingly, both of them are already being adopted by all of the leading chipmakers, which literally cannot scale to 2nm and below without them.

Cooperation Reigns In A Market That Demands Faster Innovation Cycles Than Ever

The Semicon West presentation resonated with what I’ve seen and heard for many years in my personal interactions with Applied Materials. The company has the broadest portfolio of technologies to support chip production anywhere, but it also knows that the best way to put these technologies to their best use—and keep up with insanely fast development cycles—is through cooperative efforts inside and outside the company. Over and over, you’ll hear Raja and others speak to the importance of co-design and co-innovation with partners, including chipmakers, university researchers and others. As an example, AMD senior vice president Mark Fuselier joined Raja at the Semicon West event to talk about how his company collaborates with Applied on fundamental chipmaking technologies to implement AMD’s AI chip roadmap.

It’s the same ethos that drove the creation of Applied’s Equipment and Process Innovation and Commercialization Center in Silicon Valley, which I wrote about in depth when it was announced last year. To me, the EPIC Center represents the other part of the equation for chip development. To keep up with the relentless pace of technology development—to perform atomic-level engineering at industrial scale to support the most cutting-edge applications in the world—the biggest and best operators invest way ahead of time in fundamental science and engineering. It’s the kind of work that appeals to the chip geek in me, but it’s also the seedbed for real-world breakthroughs like the ones discussed here.